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FAN5078 DDR/ACPI Regulator Combo
May 2006
FAN5078 DDR/ACPI Regulator Combo
Features
PWM regulator for VDDQ (2.5V or 1.8) Linear LDO regulator generates VTT = VDDQ/2, 1.5A Peak sink/source capability AMT / M-state support Control to generate 5V USB ACPI drive and control for 5V DUAL generation 3.3V internal LDO for 3V-ALW generation 300 kHz fixed frequency switching RDS(ON) current sensing or optional current sense resistor for precision over-current detect Internal synchronous boot diode Common Power Good signal for all voltages Input under-voltage lockout (UVLO) Thermal shutdown Latched multi-fault protection Precision reference output for ULDO controllers 24-pin 5 x 5 MLP package
Description
The FAN5078 DDR memory regulator combines a highefficiency Pulse-Width Modulated (PWM) controller to generate the memory supply voltage, VDDQ, and a linear regulator to generate termination voltage (VTT). Synchronous rectification provides high efficiency over a wide range of load currents. Efficiency is further enhanced by using the low-side MOSFET's RDS(ON) to sense current. The VDDQ PWM regulator is a sampled current mode control with external compensation to achieve fast load-transient response and provide system design optimization. The VTT regulator derives its reference and takes its power from the VDDQ PWM regulator, output. The VTT termination regulator is capable of sourcing or sinking 1.5A peak currents. In S5 M1 mode, the VDDQ switcher, VTT regulator, and the 3.3V regulators remain on. S3 mode keeps these regulators on, but also turns on an external P-Channel to provide 5V USB. A single soft-start capacitor enables controlled slew rates for both VDDQ and 3.3V-ALW outputs. PGOOD becomes true in S0 only after all regulators have achieved stable outputs. In S5 (EN = 0), the 3.3V internal LDO stays on while the other regulators are powered down.
Applications
DDR VDDQ and VTT voltage generation with ACPI support Desktop PC's Servers
Ordering Information
Part Number
FAN5078MPX
Temperature Range
-10C to 85C
Package
MLP-24 5x5mm
Packing
Tape and Reel
(c) 2006 Fairchild Semiconductor Corporation FAN5078 Rev. 1.0.0 * 05/09/06
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FAN5078 DDR/ACPI Regulator Combo
Block Diagrams
R4
+5VSB +12V
+5MAIN S3#O
Q4 C13
Q7
+5VSB SBSW
Q6
+5MAIN S3#O 3 1 16 18 17 15 13 9 10 C3 SS VCC 21 14 11 HDRV SW ISNS R3 Q2 LDRV GND FB C9 COMP VDDQ IN REF IN VTT SNS VTT OUT C7 C8
R10 Q3
5V USB
C14 C15
SBUSB# 3.3 MAIN
Q5
4
5V MAIN S4ST# BOOT Q1 C5 C2 5V DUAL
L2
S3#O EN S3#I 3.3 ALW PGOOD
ACPI CONTROL & LOGIC
2 8
CIN
C12
L1
VDDQ COUT
+5VSB
PWM
C4 R5 ILIM
12 P1 23 22 7
R2 R1 R6 C6
R9
20
VTT LDO
24 5 6
Figure 1. Typical DDR/ACPI System Regulation Schematic Components are selected for a 15A VDDQ output.
(c) 2006 Fairchild Semiconductor Corporation FAN5078 Rev. 1.0.0 * 05/11/06
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FAN5078 DDR/ACPI Regulator Combo
Table 1. BOM for Figure 1
Ref. Q1 Q2 Q3 Q4, Q6 Q5 Q7 C12,C15 C13 C14 C2 C4, C8 C3, C5 C6 C7 C9 CIN COUT L1 L2 R1,R2,R3,R9,R10 R4 R5 R6 Qty Description 1 1 1 2 1 1 2 1 1 1 2 2 1 1 1 4 3 1 1 5 1 1 1 NFET, 30V, 50A, 9m, DPAK NFET, 30V, 85A, 5m, DPAK NFET, 30V, 58A, 11m, DPAK PFET, 20V, 5.5A, 30m, SSOT6 NFET, 20V, 6.2A, 20m, SSOT6 NFET, 30V, 30A, 22m, DPAK 330uf, 10V, 20%, 110m 10nf, 50V, 10%, X7R 3.3nf, 50V, 10%, X7R 4.7uf, 25V, 20%, X5R 1.0uf, 10V, 10%, X5R 0.1uf, 16V, 10%, X7R 4.7nf, 50V, 10%, X7R 820uf, 6.3V, 20%, 36m 82pf, 50V, 5%, NPO 1200uf, 6.3V, 20%, 18m 1200uf, 6.3V, 20%, 18m IND, 1.8uH, 16A, 3.2m IND, 470nH, 16A, 2.6m 1.21K, 1% 3.9K, 5% 71.5K, 1% 15.0K, 1% Inter-Technical SC5018-1R8M Inter-Technical SC2511-R47M Mfg. and Part Number Fairchild FDD6296 Fairchild FDD8896 Fairchild FDD8880 Fairchild FDC602P Fairchild FDC637AN Fairchild FDD6612A
Contact a Fairchild representative for complete reference design and / or evaluation board. Bypass Capacitor Notes: 1. Input capacitor CIN is typically chosen based on the ripple current requirements. COUT is typically selected based on both current ripple rating and ESR requirement. See AN-6006 for these calculations. 2. C7, C12, and C15 selection is largely determined by ESR and load transient response requirements. In each case, the number of capacitors required depends on the capacitor technology chosen. Oscons can meet the requirements with less space, but higher cost, than using low-ESR electrolytics.
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FAN5078 DDR/ACPI Regulator Combo
5VSB VCC D2 BOOT CBOOT VIN Q1 S3#I S3 HDRV OVP FB RAMP CLK COMP FB S Q R RAMP S/H SW Q2 VDD LDRV PGND L OUT VDDQ COUT
EN
POR/UVLO
ADAPTIVE GATE CONTROL LOGIC
PWM
OSC
PWM
4.41K
ILIM det. ISNS SS PGOOD VDDQ IN
ISNS
RSENSE
CURRENT PROCESSING Reference and Soft Start
VREF ILIM RILIM
VDDQ
Figure 2. PWM Modulator Block Diagram
VDDQ IN
R9
S3#I
50K
REF IN
R10
VDDQ IN
+
50K
EN
VTT OUT
-
110K
VTT SNS
PGND
Figure 3. VTT Regulator Block Diagram
(c) 2006 Fairchild Semiconductor Corporation FAN5078 Rev. 1.0.0 * 05/11/06
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FAN5078 DDR/ACPI Regulator Combo
Pin Configuration
REF IN COMP GND
19
24
23
22
21
ILIM
20
SS
FB
SBUSB# S4ST# SBSW 5V MAIN VTT SNS VTT OUT
EN S3#I S3#O 3.3 ALW VCC PGOOD
18
VDDQ IN
SW
HDRV
ISNS
FAN5078MP 5x5mm MLP package (JA = 38C/W) Note: Connect P1 pad to GND.
Pin Definitions
Pin #
1 2 3 4 5 6 7 8 9 10 11 12 13
Pin
SBUSB# S4ST# SBSW 5V MAIN VTT SNS VTT OUT VDDQ IN BOOT HDRV SW ISNS LDRV PGOOD
Pin Function Description
USB Standby. Pulls low with constant current to limit slew rate in S3 if S4ST# is high. Drives a PChannel MOSFET to connect 5VSB to 5V USB. S4_STATE# Connect to system logic signal that enables 5V USB power in S3. Standby Switch. Drives the P-Channel MOSFET to power 5V DUAL from 5VSB when in S3. High in S0 and S5. 5V MAIN. When this pin is below 4.5V, transition from S3 to S0 is inhibited. VTT remote sense input. VTT regulator power output. VDDQ Input from PWM. Connect to VDDQ output voltage. This is the VTT Regulator power input. Boot. Positive supply for the upper MOSFET driver. Connect as shown in Figure 1. IC contains a boot diode to VCC. High-Side Drive. High-side (upper) MOSFET driver output. Connect to gate of high-side MOSFET. Switching Node. Return for the high-side MOSFET driver and a current sense input. Connect to source of high-side MOSFET and low-side MOSFET drain. Current Sense Input. Monitors the voltage drop across the lower MOSFET or external sense resistor for current feedback and current limiting. Low-Side Drive The low-side (lower) MOSFET driver output. Connect to gate of low-side MOSFET. Power Good Flag. An open-drain output that pulls LOW when FB is outside of a 10% range of the 0.9V reference or the VTT output is < 80% or > 110% of its reference. PGOOD goes low when the IC is in the S5 state. The power-good signal from the PWM regulator enables the VTT regulator. VCC. Provides IC bias and gate drive power. The IC is held in standby until this pin is above the UVLO threshold.
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VCC
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BOOT
LDRV
1 2 3
17 16
P1 = GND
15 4 5 6 7 8 9 10 11 12 14 13
FAN5078 DDR/ACPI Regulator Combo
Pin Definitions (Continued)
Pin
15 16 17 18 19, P1 20 21 22 23 24
Pin Name
3.3 ALW S3#O S3#I EN GND ILIM SS COMP FB REF IN
Pin Function Description
3.3V LDO Output. Internal LDO output. Turned off in S0, on in S5 or S3. S3#O Output. Open drain output which pulls the gate of the N-Channel blocking MOSFETs low in S5 and S3. This pin goes high (open) in S0. S3 Input. When LOW, turns off VTT and turns on the 3.3V regulator. Also causes S3#O to pull low to turn off blocking switch Q3, as shown in Figure 1. PGOOD is low when S3#I is LOW. ENABLE Typically tied to the system logic signal S5#. When this pin is low, the IC is in a low quiescent current state, all regulators are off and S3#O is low. GROUND for the IC is tied to this pin and is also connected to P1. Current Limit. A resistor from this pin to GND sets the current limit. Soft Start. A capacitor from this pin to GND programs the slew rate of the PWM and all LDOs during initialization and transitions between states. COMP Output of the PWM error amplifier. Connect compensation network between this pin and FB. VDDQ Feedback. The feedback from PWM output. Used for regulation as well as PGOOD, undervoltage, and over-voltage protection and monitoring. VTT Reference. Input that provides the reference for the VTT regulator. A precision internal divider from VDDQ IN (which can be overridden with external resistors) is provided.
Absolute Maximum Ratings
The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The Recommended Operating Conditions table defines the conditions for actual device operation.
Parameter
VCC SW, ISNS, HDRV, S3#O, BOOT to SW SW, ISNS, HDRV to PGND All Other Pins Junction Temperature (T ) J Storage Temperature Lead Soldering Temperature, 10 seconds I(VTT) Peak (Duration < 2mS) I(VTT) RMS Continuous Transient (t < 100nS)
Min.
Max.
6.5 28 6.5 20 20 -0.3 -20 -65 +1.5 +1.0
Units
V V V V V V C C C A A
-1 -5 -0.3 -20 -65 -1.5 -1.0
Recommended Operating Conditions
Parameter
Supply Voltage VCC I(3.3 ALW) Ambient Temperature (TA )
Conditions
Min.
4.5 -10
Typ.
5
Max.
5.5 1.25 85
Units
V A C
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FAN5078 DDR/ACPI Regulator Combo
Electrical Specifications
Recommended operating conditions; component values per Figure 1, unless otherwise noted.
Parameter
Power Supplies VCC Current: S0
Conditions
LDRV, HDRV Open, FB forced above regulation point, I(VTT) = 0, EN=1, S3#I=1 EN=1, S3#I = LOW, I(3.3) < 10mA EN=0, I(3.3) = 0 Rising VCC Falling Hysteresis Rising Falling Hysteresis to GND
Min.
Typ.
15 15 2 4.2 4,1 0.15 4.4 4.1 0.30 62 300 1.8 0.5 0.900 0.900 4.2 45 150 1.5 50
Max.
24 24 4 4.4 4.3 4.6 4.2
Units
mA mA mA V V V V V V K KHz V V V V A V mV
S3 S5 VCC UVLO Threshold
4.0 3.9 4.3 3.9 35 255
5V MAIN UVLO Threshold
5V MAIN Input Resistance Oscillator Frequency Ramp Amplitude, pk-pk(1) Ramp Offset Reference and Soft Start Internal Reference Voltage ILIM Reference Voltage Average Soft Start Current (ISS) SS Discharge Resistance SS Complete Threshold SS Complete Hysteresis PWM Converter Load Regulation FB Bias Current Under-Voltage Shutdown Over-Voltage Threshold ISNS Over-Current Threshold VDDQ IN Discharge Resistance COMP Source Current COMP Sink Current Error Amp GBW Product(1) Error Amp DC Gain(1)
345
-2A > IILIM > -18A Initial ramp after power-up During PWM / LDO soft start EN = 0
0.891 0.882
0.909 0.918
IOUT from 0 to 15A as % of set point, 2 S noise filter as % of set point RILIM= 56K EN = 0 VCOMP = 2.5V VCOMP = 2.5V
-2 -1.8 65 110 -195 20 650 100 5.5 82 -1.3 75 115 -170
+2 -0.8 80 120 -145 55
% A % % A A A MHz dB
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FAN5078 DDR/ACPI Regulator Combo
Electrical Specifications (Continued)
Parameter
PWM Output Driver HDRV Output Resistance LDRV Output Resistance PGOOD output Lower Threshold Upper Threshold PGOOD Output Low Leakage Current 3.3V LDO Regulation VTT Regulator VDDQ IN Current VREF IN to VTT Differential Output Voltage VTT Current Limit VTT Leakage Current VTT SNS Input Resistance VTT PGOOD Threshold Drop-Out Voltage Control Functions EN, S4ST# Input Threshold S3#I Input Threshold S3#I, EN, S4ST# Input Current Over-Temperature Shutdown Over-Temperature Hysteresis S3#O Output Low RDS(ON) S3#O Output High Leakage SBSW Pull-down Resistance SBSW Pull-up Resistance SBUSB# Pull-down Resistance SBUSB# pull-up resistance SBSW, SBUSB# Output Current 1.0 1.3 -1 1.25 1.5 150 25 170 1 150 900 150 550 5V MAIN < UVLO 500 1.55 1.7 1 V V A C C A nA S0 mode, IVTT=0 IVTT = 0, TA=25C IVTT = 1.25A (pulsed) Pulsed (300mS max.)(1) EN = LOW VTT SNS to GND Measured at VTT SNS IVTT = 1.5A 35 -20 -40 1.5 -20 80 -0.8 3 110 110 0.8 70 20 40 4 20 mA mV A A K % VTT REF V I(3.3) from 0-1.25A, VCC > 4.75V 3.2 3.3 3.4 V as % of set point, 2S noise filter as % of set point, 2S noise filter IPGOOD = 1.5 mA VPULLUP = 5V 86 108 92 115 0.5 1 % % V A Sourcing Sinking Sourcing Sinking 1.8 1.8 1.8 1.2 3 3 3 2
Conditions
Min.
Typ.
Max.
Units
V(S3#O) = 12V 5V MAIN OK 5V MAIN OK
300 5 200 1200 200 750
Notes: 1. Guaranteed by design and characterization, not tested in production.
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FAN5078 DDR/ACPI Regulator Combo
Circuit Description
Overview
The FAN5078 provides five functions: 1. 2. 3. A general purpose PWM regulator, typically used to generate VDDQ for DDR Memory. A low-dropout linear VTT regulator capable of sinking and sourcing 1.5A peak. Control to generate 5V DUAL using an external Nchannel to supply power from 5V MAIN in S0 and an external P-Channel to provide power from 5V Standby (5VSB) in S3. 4. 5. Drive to generate 5V USB. This signal drives a PChannel MOSFET to connect 5V USB to +5VSB in S3. An internal LDO that regulates 3.3V-ALW in S3 mode from VCC (5VSB). In S3 or S5, this regulator is capable of 1.25A peak currents with average currents limited by the thermal design of the PCB.
At initial power-up, or when transitioning from S5, the PWM regulator is disabled until 5V MAIN is above its UVLO threshold.
Table 2. ACPI states
STATE S5 S5 M1 S3 S0 EN 3.3 ALW (S5#) S3#I S4ST# SBSW SBUSB# S3#O VDDQ VTT LDO L X X H H L OFF OFF ON H L L L H L ON ON ON H L H L L L ON ON ON H H X H H H ON ON OFF 3.3 ALW LDO LDO LDO 3.3V MAIN 5V Dual OFF +5VSB +5VSB +5 MAIN 5V USB OFF OFF +5VSB +5 MAIN
Regulator Sequencing
The VCC pin provides power to all logic and analog control functions of the regulator, including: 1. 2. 3. 4. Power for the 3.3V regulator LDRV gate driver current HDRV boot diode charging current The regulator analog control and logic.
"SLEEP" or S5 state when EN is low. In S5, only the 3.3V LDO is on. If the IC is in S5 at T4, CSS is held to 0V. T4 to T5: After VDDQ is stabilized (when CSS is at about ~1.3V), an internal VDDQ OK is generated that allows the VTT LDO to start. To ensure that the VDDQ output is not subjected to large transient currents, the VTT slew rate is limited by the slew rate of the SS cap. In addition, the VTT regulator is current limited. VTT is in regulation once CSS reaches about 3.8V. S0 to S3 or S5 M1: The system signals this transition by dropping the S3#I signal. When this occurs, S3#O goes low, and the 3.3V LDO turns on. SBSW pulls low to turn on the PChannel 5V DUAL switch. SBUSB# pulls low to turn on Q6 when S4ST# is high. S3 or S5 M1 to S0: The system signals this transition by raising the S3#I signal. S0 mode is not entered until 5V MAIN OK, then the following occurs: S3#O releases SBSW and SBUSB# both pull high to turn off their P-Channel switches The 3.3V LDO turns off. In most systems, the ATX power supply is enabled when S3#I goes from high. At that time, 5V and 3.3V MAIN starts to rise. When the FAN5078's 5V MAIN pin is above its UVLO threshold, Q3 and Q5 turn on. This can cause about a 10% "dip" in both 5V DUAL and 3.3V ALW when Q3 and Q5 turn on, since at that point, 5V MAIN and 3.3V MAIN are at 90% of their regulation value.
This pin must be decoupled with a X5R ceramic capacitor (1F or larger recommended) as close as possible to the VCC pin. After VCC is above UVLO, the start-up sequence begins (see Figure 8). UVLO on VCC discharges SS and resets the IC. T0 to T3: After initial power-up, the IC ignores logic inputs for a period (T3-T0) of approximately:
T3 - T0 1.7 * C SS
(1)
where T3-T0 is in mS if CSS is in nF. At T2 (about 2/3 of the way from T1 to T3), the 3.3V-ALW LDO is in regulation. The 3.3V LDO's slew rate is limited by the discharge slope of CSS. If 3.3V MAIN has come up prior to this time, the 3.3V-ALW node is already pre-charged through the body diode of Q5 (see Figure 1). T3 to T4: The IC starts VDDQ only if 5V MAIN is above its UVLO threshold (5V MAIN OK). Provided 5V MAIN is up before T3, the IC waits about 100S before initiating soft-start on VDDQ to allow CSS time to fully discharge. The IC is in
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FAN5078 DDR/ACPI Regulator Combo
5V DUAL 5V Dual "dip" 4.4V
5V MAIN S3#O S3#I
Figure 4. S3 to S0 Transition: 5V DUAL This dip can also occur in 5V USB and 3.3V-ALW if 5V and 3.3V are not fully charged before the 5V MAIN pin exceeds its threshold. To eliminate the dip, add delay to the 5V MAIN pin, as shown below. The 5V MAIN pin on the FAN5078 does not supply power to the IC; it is only used to monitor the voltage level of the 5V MAIN supply. The pin does have a pull-down resistor impedance of about 62K and therefore requires a low value RDLY resistor (see Figure 5 below).
+5MAIN FROM ATX
RDLY
Care should also be taken to ensure that 3.3V-ALW does not glitch during the transition to S0. As shown in Figure 7, the 3.3V internal regulator turns off as soon as 5V MAIN crosses its rising threshold, releasing S3#O. While the gate capacitances of Q5, Q7, and Q3 charge sufficiently to turn Q5 on, the load current on 3.3-ALW is supplied by C12. There is an initial "ESR step" of I3.3 x ESRC12, where I3.3 is the 3.3-ALW load current. This is followed by a discharge of C12 whose I slope is proportional to 3.3 . To ensure that the drop in 3.3C12 ALW during this transition does not cause system problems, use sufficiently low ESR capacitors and a sufficiently low value for R4 to ensure that 3.3-ALW remains inside the required system tolerance.
3.3-ALW 3.3V LDO
I3.3 x ESRC12
ON
OFF
S3#O (Q5 gate)
4.4V
5V MAIN
5V MAIN
CDLY
4
S3#I
Figure 7. 3.3V-ALW Transition to S0 Figure 5. Adding Delay to 5V MAIN Another method to eliminate the potential for this dip is to instead connect the ATX power supply's PWR_OK signal to the 5V MAIN pin. Some systems cannot tolerate the long delay for PWR_OK (>100mS) to assert, hence the solution in Figure 5 may be preferable. If the PWR_OK signal is used, the voltage at the 5V MAIN pin must reach the 5V MAIN threshold. Since the internal pulldown resistance of the 5V MAIN pin is 62K, a low value pullup should be used. A lower current solution can also be used by employing the 12V supply to provide adequate pull-up capability. The circuit in Figure 6 requires that PWR_OK, 12V, and +5MAIN from the ATX are all up before allowing the IC to go to S0.
10K
S5 to S5 M1 or S3: During S5 to S3 transition, the IC pulls SBSW (or SBUSB# if enabled by S4ST#) low with a 500nA current sink to limit inrush in Q4 if 5V MAIN is below its UVLO threshold. At that time, 5V DUAL and 5V USB are discharged. The limited gate drives control the inrush current through Q4 or Q6 as they charge their respective load capacitances on 5V DUAL and 5V USB respectively. Depending on the CGD of Q4 and Q6, the current available from 5VSB, and the size of CIN and C15, C13 and C14 may be omitted.
IQ4(INRUSH) =
CIN * 5X10 -7 C13 + CGD(Q4)
+12V FROM ATX 5VS B PWR_OK
5V MAIN
C15 * 5X10-7 IQ6(INRUSH) = C14 + CGD(Q6)
(2)
4
If 5V MAIN is above its UVLO threshold, SBSW (or SBUSB# if enabled by S4ST#) is pulled down with an impedance of ~150. VDDQ and VTT do not start until 5V MAIN OK is true.
Figure 6. Using PWR_OK to Enable 5V MAIN
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FAN5078 DDR/ACPI Regulator Combo
V(UVLO)
5V SB
4V 3.8V
SS
1V
VDDQ
3.3V LDO T0 T1 T2 T3 T4 T5
Figure 8. Start-up Sequence into S0
PWM Regulator
A PSPICE model and spreadsheet calculator are available in Application Note AN-6006 for the VDDQ PWM regulator to select external components and verify loop stability. The topics covered below provide the explanation behind the calculations in the spreadsheet.
The synchronous buck converter is optimized for 5V input operation. The PWM modulator uses an average current mode control for simplified feedback loop compensation.
Oscillator
The oscillator frequency is 300Khz. The internal PWM ramp is reset on the rising clock edge.
Setting the Output Voltage
The output voltage of the PWM regulator can be set in the range of 0.9V to 80% of its power input by an external resistor divider. The internal reference is 0.9V. The output is divided down by an external voltage divider to the FB pin (for example, R1 and R2 in Figure 1). There is also a 1.3A current sourced out of FB to ensure that if the pin is open, VDDQ remains low. The output voltage therefore is: 0.9V VOUT - 0.9V = + 1.3 A R2 R1 (3a)
PWM Soft Start
When the PWM regulator is enabled, the circuit waits until the VDDQ IN pin is below 100mV to ensure that the softstart cycle does not begin with a large residual voltage on the PWM regulator output. When the PWM regulator is disabled, 40 is connected from VDDQ IN to PGND to discharge the output. The circuit waits until the FB pin is below 100mV to ensure that the soft-start cycle does not begin with a large residual voltage on the VDDQ regulator output. The voltage at the positive input of the error amplifier is limited to VCSS, which is charged with about 45A. Once CSS has charged to 0.9V, the output voltage is in regulation.
To minimize noise pickup on this node, keep the resistor to GND (R2) below 2K. In the example below, R2 is 1.82K and R1 is calculated:
R1 = R2 * (VOUT - 0.9) = 0.9 - 1.3 A 1.815K 1.82K
(3b)
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FAN5078 DDR/ACPI Regulator Combo
The time it takes SS to reach 0.9V, and VDDQ to achieve regulation is:
T0.9 0.9 X C SS 45
(4)
where T0.9 is in mS if CSS is in nF. CSS charges another 400mV before the PWM regulator's fault latch is enabled. When CSS reaches 1.2V, the VTT regulator begins its soft-start. After VTT is in regulation, PGOOD is allowed to go HIGH (open).
R5 in Figure 1 is the current limit setting resistor and comprises the only DC current path from the ILIM pin to GND. The circuit is configured so that the reference for the ULDO is presented at the positive terminal of U1 and draws negligible DC current. R3 and C1 filter noise that might be induced if there is significant PCB trace length. C1 should be placed as close as possible to the op-amp's input pin. R3 should be placed as close as possible to pin 20 of the FAN5078 and should be greater than 10K to isolate the ILIM pin from noise. Recommended values for the circuit of Figure 9:
R3 R5 C1 R1, R2 50K See AN-6006 1nF Per desired VOUT:
Reference Output for ULDO Controllers
The FAN5078's ILIM pin (pin 20) may be used as a precision 0.9V reference for external ULDO controllers, as shown in Figure 9. The ILIM pin is on during all ACPI states.
5VSB
Q1
R1 VOUT = 0.9 * 1 + R2
R3
C1
U1
20
ILIM
R5
R2
R1 COUT
VOUT
Figure 9. Using ILIM as a ULDO Reference
COMP FB 4.41K ISNS SS/EN CSS ILIM det. 2.5V I2 = ILIM*9.6
S/H V to I in + ISNS LDRV in - PGND TO PWM COMP ISNS
RSENSE
Reference and Soft Start
0.9V ILIM mirror
ILIM
RILIM
Figure 10. Current Limit / Summing Circuits
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FAN5078 DDR/ACPI Regulator Combo
Current Processing Section
The following discussion refers to Figure 10. The current through RSENSE resistor (ISNS) is sampled shortly after Q2 is turned on. That current is held and summed with the output of the error amplifier. This effectively creates a current mode control loop. RSENSE sets the gain in the current feedback loop. For stable operation, the voltage induced by the current feedback at the PWM comparator input should be set to 30% of the ramp amplitude at maximum load current and line voltage. Equation 5 estimates the recommended value of RSENSE as a function of the maximum load current ( ILOAD(MAX) ) and the value of the MOSFET's RDS(ON): R SENSE = ILOAD(MAX) * RDS(ON) * 4.41K 30% * 0.125 * VIN(MAX) - 100 (5) where RDS(ON) is the maximum RDS(ON) of the low-side MOSFET at its maximum temperature. RSENSE must, however, be kept higher than:
R SENSE(MIN) = ILOAD(MAX ) * RDS(ON) 145A - 100 (6)
variations, assuming the MOSFET's heat sinking keeps its operating die temperature below 125C. Current limit (ILIMIT) should be set sufficiently high as to allow the inductor current to rise in response to an output load transient. Typically, a factor of 1.3 is sufficient. In addition, since ILIMIT is a peak current cut-off value, multiply ILOAD(MAX) by the inductor ripple current (i.e. 20%). To account all of these variations, set ILIMIT as: ILIMIT > ILOAD(MAX) x 1.6 x 1.3 x 1.2
Q2 LDRV ISNS RSENSE R1
(8)
PGND
Figure 11. Improving Current Sensing Accuracy
More accurate sensing can be achieved by using a resistor (R1) instead of the RDS(ON) of the FET, as shown in Figure 11. This approach causes higher losses, but greater accuracy.
Gate Drive
The adaptive gate control logic translates the internal PWM control signal into the MOSFET gate drive signals, providing necessary amplification, level shifting, and shoot-through protection. It also has functions to help optimize the IC performance over a wide range of operating conditions. Since MOSFET switching time can vary dramatically from type to type and with the input voltage, the gate control logic provides adaptive dead time by monitoring the gate-to-source voltages of both upper and lower MOSFETs. The lower MOSFET drive is not turned on until the gate-to-source voltage of the upper MOSFET has decreased to less than approximately 1 volt. Similarly, the upper MOSFET is not turned on until the gate-to-source voltage of the lower MOSFET has decreased to less than approximately 1 volt. This allows a wide variety of upper and lower MOSFETs to be used without a concern for simultaneous conduction or shoot-through. There must be a low-resistance, low-inductance path between the driver pin and the MOSFET gate for the adaptive deadtime circuit to work properly. Any delay along that path subtracts from the delay generated by the adaptive dead-time circuit and shoot-through may occur.
Setting the Current Limit
ISNS is compared to the current established when a 0.9 V internal reference drives the ILIM pin. RILIM, the RDS(ON) of Q2, and RSENSE determine the current limit:
R ILIM = (100 + R SENSE ) 9.6 X ILIMIT R DS(ON)
(7)
where ILIMIT is the peak inductor current. Since the tolerance on the current limit is largely dependent on the ratio of the external resistors it is fairly accurate if the voltage drop on the switching node side of RSENSE is an accurate representation of the load current. When using the MOSFET as the sensing element, the variation of RDS(ON) causes proportional variation in the ISNS. This value not only varies from device to device, but also has a typical junction temperature coefficient of about 0.4% / C (consult the MOSFET datasheet for actual values), so the actual current limit set point decreases proportional to increasing MOSFET die temperature. A factor of 1.6 in the current limit set point should compensate for MOSFET RDS(ON)
(c) 2006 Fairchild Semiconductor Corporation FAN5078 Rev. 1.0.0 * 05/11/06
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FAN5078 DDR/ACPI Regulator Combo
Frequency Loop Compensation
The loop is compensated using a feedback network around the error amplifier.
COMP
C1 C2 R3 R1 R2 R4 C3 VREF
operation can be restored by recycling power or toggling the EN pin.
Under-Voltage Shutdown
If FB stays below the under-voltage threshold for 2S, the fault latch is set. This fault is prevented from setting the fault latch during PWM soft-start (SS < 1.3V).
VDDQ
FB
Over-Current Sensing
If the circuit's current limit signal (ILIM det shown in Figure 10) is high at the beginning of a clock cycle, a pulse-skipping circuit is activated and HDRV is inhibited. The circuit continues to pulse skip in this manner for the next 8 clock cycles. If, at any time from the 9th to the 16th clock cycle, the ILIM det is again reached, the fault latch is set. If ILIM det does not occur between cycle 9 and 16, normal operation is restored and the over-current circuit resets itself. This fault is prevented from setting the fault latch during softstart (SS < 1.3V).
Figure 12. Compensation Network
Figure 12 shows a complete Type 3 compensation network. A Type 2 compensation configuration eliminates R4 and C3 and is shown in Figure 1. Since the FAN5078 architecture employs summing current mode, Type 2 compensation can be used for most applications. For critical applications that require wide loop bandwidth and use very low ESR output capacitors, Type 3 compensation may be required. The PSPICE model and spreadsheet calculator of AN-6006 can be used to calculate these component values. Transient response during a rapid decrease in ILOAD can be improved by adding a pull-down resistor (> 5K) from the COMP pin to GND.
PGOOD Signal
PGOOD monitors the status of the PWM output as well as VTT. PGOOD remains low unless all of the conditions below are met: SS is above 3.5V Fault latch is cleared FB is between 90% and 110% of VREF VTT is in regulation.
Figure 13. Over-Current Protection Waveforms
OVP / HS Fault / FB short to GND detection
A HS Fault is detected when there is more than 0.5V from SW to PGND 350nS after LDRV reaches 4V (same as the current sampling time). OVP fault detection occurs if FB > 115% VREF for 16 clock cycles. During soft-start, the output voltage could potentially "run away" if either the FB pin is shorted to GND or R1 is open. This fault is detected if the following condition persists for more than 14S during soft-start: VDDQ IN (PWM output voltage) > 1V FB < 100mV Any of these faults sets the fault latch, even during the SS time (SS < 1.2V).
Protection
The converter output is monitored and protected against extreme overload, short circuit, over-voltage and undervoltage conditions. An internal fault latch is set for any fault intended to shut down the IC. When the fault latch is set, the IC discharges its output by driving LDRV high until VDDQ IN < 0.5V. LDRV then goes low until VDDQ IN > 0.8V. This discharges VDDQ without causing undershoot (negative output voltage). To discharge the output capacitors, a 40 load resistor is switched in from VDDQ IN to PGND whenever the IC is in fault condition or when EN is low. After a latched fault,
(c) 2006 Fairchild Semiconductor Corporation FAN5078 Rev. 1.0.0 * 05/11/06 14
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FAN5078 DDR/ACPI Regulator Combo
To ensure that FB pin open does not cause a destructive condition, a 1.3A current source ensures that the FB pin is high if open. This causes the regulator to keep the output low and eventually results in an under-voltage fault shutdown (after PWM SS completes).
COMP 1.3A FB ISS SS
FAN5078 Design Tools
AN-6006 provides a PSPICE model and spreadsheet calculator for the PWM regulator, simplifying external component selections, and verifying loop stability. The spreadsheet calculator can be used to calculate all external component values for the FAN5078. The spreadsheet calculates compensation components that can be verified in the PSPICE model to ensure stability. The PSPICE model in AN-6006 simulates both loop stability (Bode Plot) and transient analysis, and can be customized for a wide variety of applications and external component configurations. As an initial step, define: Output voltage
- + E/A +
4.41K RAMP
- + PWM +
VREF
ISNS
Figure 14. SS Clamp and FB Open Protection
Maximum PWM output load current Maximum load transient current and maximum allowable output drop during load transient RDS(ON) of the low-side MOSFET (Q2) Maximum allowable output ripple.
Over-Temperature Protection
The chip incorporates an over-temperature protection circuit that shuts the chip down when a die temperature of about 150C is reached. Normal operation is restored when the die temperature falls below 125C with internal Power On Reset asserted, resulting in a full soft-start cycle. To accomplish this, the over-temperature comparator discharges the SS pin.
Power MOSFET Selection
For a complete analysis of MOSFET selection and efficiency calculations, see Application Note AN-6005: Synchronous Buck MOSFET Loss Calculations with Excel Model.
VTT Regulator Section (Figure 3)
The VTT regulator includes an internal resistor divider (50K for each resistor) from the output of the PWM regulator. If the REF IN pin is left open, the divider produces a voltage 50% of VDDQ IN. Using a low impedance external precision voltage divider produces greater accuracy. The VTT regulator is enabled when S3#I is HIGH and the PWM regulator's internal PGOOD signal is true. The VTT regulator also includes its own PGOOD signal, which is high when VTT SNS > 90% of REF IN.
3.3V and VTT LDO Output Capacitors
For stability, use at least 100F for 3.3V-ALW bypass capacitor with a minimum ESR of 20m. The VTT output is typically bypassed with 820F with at least 30m ESR.
(c) 2006 Fairchild Semiconductor Corporation FAN5078 Rev. 1.0.0 * 05/11/06
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FAN5078 DDR/ACPI Regulator Combo
Dimensional Outline Drawing
Notes: 1. Conforms to JEDEC registration number MO-220, variation WHHC, dated Aug/2002. 2. Dimensions are in millimeters. 3. Dimensions and tolerances per ASME y14.5-1994.
(c) 2006 Fairchild Semiconductor Corporation FAN5078 Rev. 1.0.0 * 05/11/06
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